A computer system may comprise a processor, which may include a core area and an uncore area. The core area may include one or more processing cores, caches (L1 and L2, for example), line-fill buffers and the uncore area may comprise last level caches, a memory controller, and such other blocks. The processor power management techniques aim at reducing the power consumed by the core area. In one prior approach, an activity factor in the core area is measured and a power value (actual power consumption value) corresponding to the activity factor is determined. Then, voltage and/or frequency operating point may be varied based on a comparison between the actual power consumption value and an allowable power value. The power management technique may lower the voltage and/or frequency operating point after detecting that the actual power consumption value is equal to or higher than the allowable power value. However, a specific amount of time would be incurred between the point at which the high activity is detected and the point at which the voltage and/or frequency operating point is actually lowered. In between these two points, the computer system may operate in high power state and high activity state as well. To avoid such a situation, the processor (or the part) has to be binned at a lower voltage and frequency point (V/F) point.
In another prior approach, the voltage and/or frequency operating points may be selected based on the processor power saving (P) states and boost modes, which may modulate the voltage and/or frequency operating points based on the actual power consumed value. The above approaches rely on voltage operation range to increase or decrease the power and performance through frequency. With each new generation of processors, the voltage range is reduced as VCCmax is lowered for gate-oxide reliability while VCCmin remains almost constant. The above approaches are reactive in nature to the over power condition. The power management techniques discussed above respond only after the processor has reached a high thermal or power state. As a result, the time taken (or latency) to actually change the voltage and/or frequency operating point in response to a change in the thermal or power state is substantial and there is a need to reduce the latency.
Also, on the other hand, the modern processors are targeted for many core designs and these cores are coupled to a common uncore area. With the advancements in the process technology, the uncore area within the processor is growing larger in size. The uncore areas in modern processors may include many functional and logical blocks (e.g., memory controller, last level caches, home agents, routing agents, caching agents, power control units, interfaces, and such other blocks) and may typically operate on a different power plane than that of the core area. Desirably, these processors need to consume low idle power, for example, to reduce the total energy consumed and/or improving the battery life. However, the power consumed by such larger uncore area has reached considerable levels (close to 50% of the total power consumed by the processor).
Management of power consumption in the uncore area has become more important than ever. The power management in the uncore area poses additional challenges as there are no well defined sleep states (for example, C0 to C6/C7) like that of the core area. Especially, when the core area is in deep sleep state such as a C3, C6/C7 or any other similar states (referred to as package C-state), the core architecture states are saved in the uncore area and the core voltage is reduced to a substantially minimum value using per core power gate transistors (PGT) or embedded power gates (EPG). Under this condition, the idle power consumption by the core area is almost zero and the idle power consumed by the uncore area is substantial. Also, the uncore area, unlike the core area, has to be active to service any external requests within a specified latency. Many of these processors are designed for multi-socket configuration with distributed memory coupled to the multiple sockets. Using power optimization techniques such as voltage and frequency scaling may affect the snoops or memory access response to the peer sockets or system agent response latency. Thus, the current processors do not use voltage/frequency scaling techniques to conserve power in the uncore area while the core area in package C-state. As a result, the processor package idle power is as high as 20-40% of the thermal design power (TDP) power. Thus, there is a need for improved power management techniques in both the core and the uncore areas of the processor.